PART 1
MSX-VIDEO DATA PROCESSOR
V9938
USER'S MANUAL
BASIC INPUT AND OUTPUT
1. Accessing the Control Registers
There are two ways to set data in the MSX-VIDEO control registers (R#0 to R#46), which we will describe below.
1.1 Direct access
Output the data and the register number in sequence to port #1. Since this order is always used, be careful when you access the MSX-VIDEO for an interrupt routine.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Port #1 First byte | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DATA |
| Second byte | 1 | 0 | R5 | R4 | R3 | R2 | R1 | R0 | REGISTER # |
1.2 Indirect access
Specify the register number in control register R#17 (Control Register Pointer).
First set the register number in R#17 (using direct addressing) by sending data to port #3. When you set the data in R#17, you can also set its MSB (AII, the autoincrement bit) to control autoincrementing. The data in R#17 cannot be changed by indirect addressing.
If autoincrement is prohibited, the contents of R#17 will be unchanged, and thus you do not have to reset R#17.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Register #17 | AII | 0 | R5 | R4 | R3 | R2 | R1 | R0 | REGISTER # |
|
├── 1: Auto increment inhibit └── 0: Auto increment on |
|||||||||
| Port #3 First byte | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DATA |
| Port #3 Second byte | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DATA |
| ... | |||||||||
| Port #3 nth byte | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DATA |
2. Accessing the Palette Registers
To set data in the MSX-VIDEO palette registers (P#0 to P#15/9 bit), you must first set the palette register number in register R#16 (Color palette address pointer) and subsequently output the two bytes of data (in order) through port #2.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Register #16 | 0 | 0 | 0 | 0 | C3 | C2 | C1 | C0 | Palette # |
| Port #2 First byte | 0 | R2 | R1 | R0 | 0 | B2 | B1 | B0 | DATA |
| Red data | Blue data | ||||||||
| Port #2 Second byte | 0 | 0 | 0 | 0 | 0 | G2 | G1 | G0 | DATA |
| Green data | |||||||||
(Editor's note: R#16 increases after every second data byte written)
3. Accessing the Status Registers
To read the status registers of the MSX-VIDEO (S#0 to S#9), you must first set the register number in R#15 (Status register pointer) and read the data through Port #1.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Register #15 | 0 | 0 | 0 | 0 | S3 | S2 | S1 | S0 | Status register |
| Port #1 Read data | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DATA |
4. Accessing the Video RAM
A Video RAM of 128K bytes plus an expansion RAM of 64K bytes can be connected to the MSX-VIDEO. The memory maps for these cases are shown in the map below.
Address counter
┌─────────┐ 1FFFFH
│ │ │
│ │ │
│ │ │
│ │ │
├─────────┤ 0FFFFH ┌─────────┐
│ │ │ │ │
│ │ │ │ │
│ │ │ │ │
│ │ │ │ │
└─────────┘ 00000H └─────────┘
Video RAM Expansion RAM
(For display) (For data I/O registers)
Accessing memory
To access memory, follow the procedure below.
- Switch banks (VRAM to Expansion RAM)
- Set the address counter (A16 to A14)
- Set the address counter (A7 to A0)
- Set the address counter (A13 to A8), and specify read or write
- Read or write the data
1. Switching banks (VRAM to Expansion RAM)
Since the contents of R#45 (Argument register) do no change each time that memory is accessed, it is not necessary to respecify bit 6 of register R#45 (which specifies banking) every time that you are to do banking.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Register #45 | 0 | MXC | MXD | MXS | DIY | DIX | EQ | MAJ | Argument register |
|
├── 1: Expansion RAM └── 0: Video RAM |
|||||||||
2. Setting the address counter (A16-A14)
Set the high-order three bits (A16 to A14) of the address counter using register R#14 (VRAM Access base address register).
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Register #14 | 0 | 0 | 0 | 0 | 0 | A16 | A15 | A14 | VRAM Access base address register |
3. Setting the address counter (A7 to A0)
Set the low-order eight bits (A7 to A0) of the address counter by outputting data to Port #1.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Port #1 | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | First byte |
4. Setting the address counter (A13 to A8) and specifying read or write
Set the remaining six bits (A13 to A8) of the address counter and specify read or write by outputting data to Port #1.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Port #1 | X | X | A13 | A12 | A11 | A10 | A9 | A8 | Second byte |
| 0 | 0: | Read | |||||||
| 0 | 1: | Write | |||||||
5. Reading or writing data
Since the address counter is automatically incremented when data is read from or written to Port #0, you may continually access blocks of data.
- To access the VRAM, you can also use commands. These commands will be explained in a later chapter.
- Refer to the data sheet for access timings.
REGISTER FUNCTIONS
1. CONTROL REGISTERS
#0 to #23 (Write only)
#32 to #46 (Write only)
1.1 Mode Registers
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#0 | 0 | DG | IE2 | IE1 | M5 | M4 | M3 | 0 | Mode Register 0 |
| R#1 | 0 | BL | IE0 | M1 | M2 | 0 | SI | MAG | Mode Register 1 |
| R#8 | MS | LP | TP | CB | VR | 0 | SPD | BW | Mode Register 2 |
| R#9 | LN | 0 | S1 | S0 | IL | EO | DC | Mode Register 3 |
| R#0 | DG: | Sets the color bus to input mode, and inputs data into the VRAM. |
| IE2: | Enables interrupt from Lightpen by Interrupt Enable 2. | |
| IE1: | Enables interrupt from Horizontal scanning line by Interrupt Enable 1. | |
| M5: | Used to change the display mode. | |
| M4: | Used to change the display mode. | |
| M3: | Used to change the display mode. |
| R#1 | BL: | When 1, screen display enabled. When 0, screen disabled. |
| IE0: | Enables interrupt from Horizontal scanning line by Interrupt Enable 0. | |
| M1: | Used to change the display mode. | |
| M2: | Used to change the display mode. | |
| SI: | When 1, sprite size is 16 x 16. When 0, 8 x 8. | |
| MA: | Sprite expansion; when 1: expanded. When 0, normal. |
| R#8 | MS: | When 1, sets the color bus to input mode and enables mouse. When 0, sets the color bus to output mode and disables mouse. |
| LP: | When 1, enables light pen. When 0, disables light pen. | |
| TP: | Sets the color of code 0 to the color of the palette. | |
| CB: | When 1, sets the color bus to input mode. When 0, sets the color bus to output mode. |
|
| VR: | Selects the type of Video RAM. 1 = 64K x 1 bit or 64K x 4 bits. 0 = 16K x 1 bit or 16K x 4 bits. |
|
| SPD: | When 1, disables display of sprites. When 0, displays sprites. | |
| BW: | When 1, sets black and white in 32 tones. When 0, sets color (available only with a composite encoder). |
| R#9 | LN: | When 1, sets the horizontal dot count to 212. When 0, sets the horizontal dot count to 192. |
| S1: | Selects simultaneous mode. | |
| S0: | Selects simultaneous mode. | |
| IL: | When 1, interlace (Complete NTSC timing) When 0, non-interlace (Incomplete NTSC timing) |
|
| EO: | When 1, displays two graphic screens interchangably by Even field/Odd field. When 0, displays the same graphic screen by Even field/Odd field. |
|
| When 1, PAL (313 lines); when 0, NTSC (262 lines). (For RGB output only) | ||
| DC: | When 1, sets *DLCLK to input mode; when 0, sets *DLCLK to output mode. |
1.2 Table Base Address Registers
The table base address registers are a set of registers to declare the addresses of tables in the VRAM to be used by MSX-VIDEO.
Note that when these registers are accessed, the control codes that the screen may receive depends on the display mode. For this purpose, you must mask the unwanted bits.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#2 | 0 | A16 | A15 | A14 | A13 | A12 | A11 | A10 | Pattern name table base address register |
| R#3 | A13 | A12 | A11 | A10 | A9 | A8 | A7 | A6 | Color table base address register low |
| R#10 | 0 | 0 | 0 | 0 | 0 | A16 | A15 | A14 | Color table base address register high |
| R#4 | 0 | 0 | 0 | 0 | 0 | A16 | A15 | A14 | Pattern generator table base address register |
| R#5 | A14 | A13 | A12 | A11 | A10 | A9 | A8 | A7 | Sprite attribute table base address register low |
| R#11 | 0 | 0 | 0 | 0 | 0 | 0 | A16 | A15 | Sprite attribute table base address register high |
| R#6 | 0 | 0 | A16 | A15 | A14 | A13 | A12 | A11 | Sprite attribute table base address register high |
1.3 Color Registers
The color registers are used to control the MSX-VIDEO's text and background screen colors as well as blinking, etc.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└───┴───┴───┴───┴───┴───┴───┴───┘ color register
TC3 to TC0: Specifies the text color according to TEXT 1
and TEXT 2 modes.
BD3 to BD0: Specifies the back drop color in all display
modes.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#12 | T23 | T22 | T21 | T20 | BC3 | BC2 | BC1 | BC0 | Text color/Back color register |
In TEXT 2 mode, if the attributes for blinking are set, the color set in this register and set in R#7 are displayed alternately.
T23 to T20: Specifies the color of part 1 of the pattern.
BC3 to BC0: Specifies the color of part 0 of the pattern.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#13 | ON3 | ON2 | ON1 | ON0 | OF3 | OF2 | OF1 | OF0 | Blinking period register |
In the bit map modes of GRAPH4 to GRAPH7, the two pages are alternately displayed (blinked). Place data in this register to set the display page to an odd page to begin blinking. This register is also used in the TEXT2 mode.
ON3 to ON0: Display time for even page
OF3 to OF0: Display time for odd page
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Color burst register 1 |
| R#21 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | Color burst register 2 |
| R#22 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Color burst register 3 |
The above values are preset when the power is applied. If all values in the above three registers are set to 0, the color burst signal of the composite video output will be erased.
If the above values are subsequently reset to the preset values, the normal color burst signal will be output.
1.4 Display Registers
The display registers are used to control the display position on the CRT.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#18 | V3 | V2 | V1 | V0 | H3 | H2 | H1 | H0 | Display adjust register |
The above register is used to adjust the display position on the CRT.
H = 7 . . . H = 1, H = 0, H = 15 . . . H = 8
(Left) (Center) (Right)
V = 8 . . . V = 15, V = 0, V = 1 . . . V = 7
(Bottom) (Center) (Top)
(Editor's note: modifying this value while executing a VDP command when the sprites are disabled will result in a corrupted byte)
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#23 | DO7 | DO6 | DO5 | DO4 | DO3 | DO2 | DO1 | DO0 | Display offset register |
The above register sets the location of the line to begin display.
VRAM (Line)
TOP ┌────────────┐ 0
│ │
│ CRT Screen │
│ │
BOTTOM ├────────────┤ 192 or 212 R#23 = 0
│ │
└────────────┘ 255
┌────────────┐ 0
│ │
│ CRT Screen │
│ │
BOTTOM ├────────────┤ 136 or 156 R#23 = 200
│ │
TOP ├────────────┤ 200
│ CRT Screen │
└────────────┘ 255
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#19 | IL7 | IL6 | IL5 | IL4 | IL3 | IL2 | IL1 | IL0 | Interrupt line register |
You may specify interrupts when the MSX-VIDEO begins to display a specified scanning line. To enable the interrupt, use the above register to set the scanning line.
1.5 ACCESS REGISTERS
The access registers are a set of registers used when accessing the MSX-VIDEO registers or the VRAM.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#14 | 0 | 0 | 0 | 0 | 0 | A16 | A15 | A14 | VRAM Access base address register |
When accessing the MSX-VIDEO and the Video RAM (VRAM), set the high-order three bits of the address in the VRAM access base address register.
When data is set in this register, and the VRAM is accessed, if there is a carry from A13, the data in the register is automatically incremented. In GRAPHIC1, GRAPHIC2, MULTICOLOR, and TEXT1 modes, the data in the register is not automatically incremented.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#15 | 0 | 0 | 0 | 0 | S3 | S2 | S1 | S0 | Status register pointer |
When reading the MSX-VIDEO status registers (S#0 to S#9), set the contents of the status register pointer.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#16 | 0 | 0 | 0 | 0 | C3 | C2 | C1 | C0 | Color palette address register |
When setting the color palette of the MSX-VIDEO, set the number of the palette in the Color palette address register.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#17 | AII | 0 | RS5 | RS4 | RS3 | RS2 | RS1 | RS0 | Control register pointer |
In the MSX-VIDEO, the above control register pointer may be used to access another register. In addition, according to the setting of the AII bit, the data van be automatically incremented.
AII = 1: Auto increment disabled
AII = 0: Auto increment enabled
1.6 COMMAND REGISTERS
The following command registers are used when executing a command on the MSX-VIDEO. Details on the use of these command registers will be presented in a later chapter.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#32 │SX7│SX6│SX5│SX4│SX3│SX2│SX1│SX0│ Source X low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#33 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │SX8│ Source X high register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#34 │SY7│SY6│SY5│SY4│SY3│SY2│SY1│SY0│ Source Y low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#35 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │SY9│SY8│ Source Y high register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#36 │DX7│DX6│DX5│DX4│DX3│DX2│DX1│DX0│ Destination X low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#37 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │DX8│ Destination X high register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#38 │DY7│DY6│DY5│DY4│DY3│DY2│DY1│DY0│ Destination Y low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#39 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │DY9│DY8│ Destination Y high register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#40 │NX7│NX6│NX5│NX4│NX3│NX2│NX1│NX0│ Number of dots X low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#41 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │NX8│ Number of dots X high register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#42 │NY7│NY6│NY5│NY4│NY3│NY2│NY1│NY0│ Number of dots Y low register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#43 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │NY9│NY8│ Number of dots Y high register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#44 │CH3│CH2│CH1│CH0│CL3│CL2│CL1│CL0│ Color register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#45 │ 0 │MXC│MXD│MXS│DIY│DIX│EQ │MAJ│ Argument register
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#46 │CM3│CM2│CM1│CM0│LO3│LO2│LO1│LO0│ Command register
└───┴───┴───┴───┴───┴───┴───┴───┘
2. STATUS REGISTERS #0 to #9 (Read only)
The following status registers are read-only registers for reporting the status when the MSX-VIDEO is read.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#0 │ F │5S │ C │Fifth sprite number│ Status register 0
└───┴───┴───┴───┴───┴───┴───┴───┘
F: Vertical scanning interrupt flag
When S#0 is read, this flag is reset.
5S: Flag for the fifth sprite
Five sprites are aligned on the first horizontal line (In
the G3 to G7 modes, 9 sprites are allowed)
C: Collision flag
Two sprites have collided.
Fifth sprite number:
The number of the fifth (or ninth) sprite.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#1 │FL │LPS│ Identification # │FH │ Status register 1
└───┴───┴───┴───┴───┴───┴───┴───┘
FL: Lightpen flag (Lightpen flag set)
If the lightpen is to detect light, this bit as well as the
IE2 bit must both set in order for an interrupt to be
enabled. When S#1 is read, FL is reset.
Mouse switch 2 (Mouse flag set)
The second switch on the mouse was pressed.
In this case, when S#1 is read, FL is not reset.
LPS: Lightpen switch (Lightpen flag set)
The lightpen switch was pressed.
In this case, when S#1 is read, LPS is not reset.
Mouse switch 1 (Mouse flag set)
The first switch on the mouse was pressed.
In this case, when S#1 is read, LPS is not reset.
Identification number:
The identification number (ID #) of the MSX-VIDEO.
(Editor´s note: 0 if V9938, 1 if V9948, 2 if V9958)
FH: Horizontal scanning interrupt flag
Horizontal scanning interrupt (which is specified in R#19)
flag. If IE1 is set, an interrupt is enabled. When S#1
is read, FH is reset.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#2 │TR │VR │HR │BD │ 1 │ 1 │EO │CE │ Status register 2
└───┴───┴───┴───┴───┴───┴───┴───┘
TR: Transfer ready flag
When the CPU sends commands to the VRAM and other devices,
the CPU checks this flag while transferring data. When this
flag is set to 1, transfer may be done.
VR: Vertical scanning line timing flag
During vertical scanning, this flag is set to 1.
HR: Horizontal scanning line timing flag
During horizontal scanning, this flag is set to 1.
BD: Boundary color detect flag
When the search command is executed, this flag detects
whether the boundary color was detected or not.
EO: Display field flag
When 0, indicates the first field.
When 1, indicates the second field.
CE: Command execution flag
Indicates that a command is being executed.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#3 │X7 │X6 │X5 │X4 │X3 │X2 │X1 │X0 │ Column register low
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
S#4 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │X8 │ Column register high
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
S#5 │Y7 │Y6 │Y5 │Y4 │Y3 │Y2 │Y1 │Y0 │ Row register low
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
S#6 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │EO │Y8 │ Row register high
└───┴───┴───┴───┴───┴───┴───┴───┘
The above registers are set to indicate the collision location of sprites, the location of lightpen detection, and the relative movement of the mouse.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#7 │C7 │C6 │C5 │C4 │C3 │C2 │C1 │C0 │ Color register
└───┴───┴───┴───┴───┴───┴───┴───┘
The above color register is used when the POINT and VRAM to CPU commands are executed. The VRAM data is set in this register.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
S#8 │BX7│BX6│BX5│BX4│BX3│BX2│BX1│BX0│ Border X register low
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
S#9 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │BX8│ Border X register high
└───┴───┴───┴───┴───┴───┴───┴───┘
When the search command is executed and the border color has been detected, the X coordinate is set in the above registers.
TEXT 1 MODE
Characteristics
- Pattern size : 6 dots (w) x 8 dots (h) - Patterns : 256 types - Screen pattern count : 40 (w) x 24 (h) patterns - Pattern colors : Two colors out of 512 colors (per screen) - VRAM area per screen : 4K bytes
Controls
- Pattern font : VRAM pattern generator table - Screen pattern location : VRAM pattern name table - Pattern color code 1 : High-order four bits of R#7 - Pattern color code 0 : Low-order fout bits of R#7 - Background color code : Low-order fout bits of R#7
Initial settings
1. Mode and register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 0*│ 0*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 1*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in TEXT 1 mode
** Indicates negative logic
All other bits are set accordingly
2. Pattern Generator Table Settings
- The pattern generator table is an area that stores the pattern fonts.
- Each pattern had a number from PN0 to PN255.
- The font for each pattern is constructed from 8 bytes, and the lower two bits of each of the eight bytes is not displayed.
- Set the beginning (head) address of the pattern generator table is register R#4.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#4 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Pattern generator table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern generator table
(X=1, O=0)
┌┬──────── These bits are not displayed.
││
MSB 76543210 LSB
0 OOXOOOOO ─────┐
1 OXOXOOOO │
2 XOOOXOOO │
3 XOOOXOOO ├─── Pattern number 0
4 XXXXXOOO │
5 XOOOXOOO │
6 XOOOXOOO │
7 OOOOOOOO ─────┘
8 XXXXOOOO ─────┐
9 XOOOXOOO │
10 XOOOXOOO │
11 XXXXOOOO ├─── Pattern number 1
12 XOOOXOOO │
13 XOOOXOOO │
14 XXXXOOOO │
15 OOOOOOOO ─────┘
. . .
. . .
. . .
2040 XOXOXOOO ─────┐
2041 OXOXOXOO │
2042 XOXOXOOO │
2043 OXOXOXOO ├─── Pattern number 0
2044 XOXOXOOO │
2045 OXOXOXOO │
2046 XOXOXOOO │
2047 OXOXOXOO ─────┘
3. Pattern name table settings
- The pattern name table is composed of one byte for each screen pattern. Each byte specifies a unique pattern.
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│A14│A13│A12│A11│A10│ Pattern name table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern name table
│ │
├─────────┤ Base address
│ ( 0, 0) │ 0 0 1 2 3 . . 39 X
├─────────┤ ┌────┬────┬────┬────┬ ┬────┐
│ ( 1, 0) │ 1 0 │ 0│ 1│ 2│ 3│ . . │ 39│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
│ ( 2, 0) │ 2 1 │ 40│ 41│ 42│ 43│ . . │ 79│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
¦ ¦ . . . . . . . . .
¦ ¦ . . . . . . . . .
¦ ¦ . ├────┼────┼ ──┼────┤
├─────────┤ 22 │ 880│ 881│ . . . . │ 919│
│ (39, 0) │ 39 ├────┼────┼ ──┼────┤
├─────────┤ 23 │ 920│ 921│ . . . . │ 959│
│ ( 0, 1) │ 40 └────┴────┴ ──┴────┘
├─────────┤ Y
¦ ¦ .
¦ ¦ . Screen display correspondence
¦ ¦ .
├─────────┤
│ (39,23) │ 959
├─────────┤
4. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop color
└──┬┴──┬┴──┬┴──┬┴──┬┴──┬┴──┬┴──┬┘ register
│ │ │ │ └───┴───┴───┴── Specifies pattern color
│ │ │ │ code 0 or back drop color
└───┴───┴───┴────────────────── Specifies pattern color
code 1
Example of VRAM allocation in TEXT 1 mode
00000H ┌──────────┐ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Name │ R#2 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │
│ Table 0 │ └───┴───┴───┴───┴───┴───┴───┴───┘
│ │ A16 A15 A14 A13 A12 A11 A10
003C0H ├──────────┤
│ │
00800H ├──────────┤ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Generator│ R#4 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │
│ Table 0 │ └───┴───┴───┴───┴───┴───┴───┴───┘
│ │ A16 A15 A14 A13 A12 A11
│ │
01000H ├──────────┤ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Name │ R#2 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 0 │ 0 │
│ Table 1 │ └───┴───┴───┴───┴───┴───┴───┴───┘
│ │ A16 A15 A14 A13 A12 A11 A10
│ │
013C0H ├──────────┤
│ │
│ │
01800H ├──────────┤ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Generator│ R#4 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 1 │
│ Table 1 │ └───┴───┴───┴───┴───┴───┴───┴───┘
│ │ A16 A15 A14 A13 A12 A11
02000H ├──────────┤
. .
. . A maximum of 32 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
TEXT 2 MODE
Characteristics
- Pattern size : 6 dots (w) x 8 dots (h)
- Patterns : 256 types
- Screen pattern count : 80 (w) x 24 (h) patterns
80 (w) x 26.5 (h) patterns
- Pattern blinking : Possible for each character
- Pattern colors : Two colors out of 512 colors (per screen),
four if using blinking
- VRAM area per screen : 8K bytes
Controls
- Pattern font : VRAM pattern generator table
- Screen pattern location : VRAM pattern name table
- Blink attributes : VRAM color table
- Pattern color code 1 : High-order four bits of R#7
- Pattern color code 0 : Low-order four bits of R#7
- Background color code : Low-order four bits of R#7
- Pattern color code 1 : High-order four bits of R#12
(used for blinking)
- Pattern color code 0 : Low-order four bits of R#12
(used for blinking)
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 1*│ 0*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 1*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in TEXT 2 mode
** Indicates negative logic
In this display mode, if LN is set to 1, 26.5 lines are selected,
and if LN is set to 0, 24 lines are selected.
All other bits are set accordingly.
2. Pattern Generator Table Settings
- The pattern generator table is an area that stores the pattern fonts.
- Each pattern has a number from PN0 to PN255.
- Set the beginning (head) address of the pattern generator table in register R#4
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#4 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Pattern generator table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
- The font for each pattern is constructed from 8 bytes, and the lower two bits of each of the eight bytes is not displayed.
Pattern generator table
(X=1, O=0)
┌┬──────── These bits are not displayed.
││
MSB 76543210 LSB
0 OOXOOOOO ─────┐
1 OXOXOOOO │
2 XOOOXOOO │
3 XOOOXOOO ├─── Pattern number 0
4 XXXXXOOO │
5 XOOOXOOO │
6 XOOOXOOO │
7 OOOOOOOO ─────┘
8 XXXXOOOO ─────┐
9 XOOOXOOO │
10 XOOOXOOO │
11 XXXXOOOO ├─── Pattern number 1
12 XOOOXOOO │
13 XOOOXOOO │
14 XXXXOOOO │
15 OOOOOOOO ─────┘
. . .
. . .
. . .
2040 XOXOXOOO ─────┐
2041 OXOXOXOO │
2042 XOXOXOOO │
2043 OXOXOXOO ├─── Pattern number 255
2044 XOXOXOOO │
2045 OXOXOXOO │
2046 XOXOXOOO │
2047 OXOXOXOO ─────┘
3. Pattern name table settings
- The pattern name table is composed of one byte for each screen pattern. Each byte specifies a unique pattern.
- If LN is set to 0, the screen display pattern is 80 (W) x 24 (H); and if LN is set to 1, the screen display pattern is 80 (W) x 26.5 (H). The upper half of the 27th pattern is displayed.
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│A14│A13│A12│ 1 │ 1 │ Pattern name table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern name table
│ │
├─────────┤ Base address
│ ( 0, 0) │ 0 0 1 2 3 . . 79 X
├─────────┤ ┌────┬────┬────┬────┬ ┬────┐
│ ( 1, 0) │ 1 0 │ 0│ 1│ 2│ 3│ . . │ 79│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
│ ( 2, 0) │ 2 1 │ 80│ 81│ 82│ 83│ . . │ 159│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
¦ ¦ . . . . . . . . .
¦ ¦ . . . . . . . . .
¦ ¦ . ├────┼────┼ ──┼────┤
├─────────┤ 25 │2000│2001│ . . . . │2079│
│ (79, 0) │ 79 ├────┼────┼ ──┼────┤
├─────────┤ 26 │2080│2081│ . . . . │2159│
│ ( 0, 1) │ 80 └────┴────┴ ──┴────┘
├─────────┤ Y
¦ ¦ .
¦ ¦ . Screen display correspondence
¦ ¦ .
├─────────┤
│ (79,26) │ 2159
├─────────┤
4. Color table settings
- In TEXT 2 mode, each pattern has a separate bit for the attribute area, and if this bit is set to 1, the pattern blink attribute will be set.
- Set the beginning (head) address of the color table in registers R#3 and R#10.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#3 │A13│A12│A11│A10│A9 │ 1 │ 1 │ 1 │ Color table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#10 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│A14│ base address registers
└───┴───┴───┴───┴───┴───┴───┴───┘
Color table
MSB 7 6 5 4 3 2 1 0 LSB ┌───────┬───────┬───────┬───────┬───────┬───────┬───────┬───────┐ 0│( 0, 0)│( 1, 0)│( 2, 0)│( 3, 0)│( 4, 0)│( 5, 0)│( 6, 0)│( 7, 0)│ Base ├───────┼───────┼───────┼───────┼───────┼───────┼───────┼───────┤ address 1│( 8, 0)│( 9, 0)│(10, 0)│(11, 0)│(12, 0)│(13, 0)│(14, 0)│(15, 0)│ ├───────┼───────┼───────┼───────┼───────┼───────┼───────┼───────┤ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ├───────┼───────┼───────┼───────┼───────┼───────┼───────┼───────┤ 269│(72,26)│ . │ . │ . │ . │ . │ . │(79,26)│ └───────┴───────┴───────┴───────┴───────┴───────┴───────┴───────┘
5. Color register settings
- Set the color for pattern 1 in the high-order bits of register R#7.
- Set the color for pattern 0 in the low-order bits of register R#7.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└───┴───┴───┴───┴───┴───┴───┴───┘ color register
- Set the blink attribute for the corresponding pattern by setting an alternate color code in register R#12. The pattern will be blinked by using the color codes set in register R#7 and R#12.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#12 │T23│T22│T21│T20│BC3│BC2│BC1│BC0│ Text color/Back color
└───┴───┴───┴───┴───┴───┴───┴───┘ register
6. Blink register settings
- The color codes set in registers R#7 and R#12 will be alternately displayed for blinking; however, the blinking period attribute (time on and time off) can also be set in register R#13.
┌────────────────┐ ┌─────────────
│ │ │
│ R#12 │ R#7 │ R#12
│ │ │
─────────┘ └────────────────┘
│◄── On time ───►│◄── Off time ──►│
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#13 │ON3│ON2│ON1│ON0│OF3│OF2│OF1│OF0│ Blinking period register
└──┬┴───┴───┴──┬┴──┬┴───┴───┴──┬┘
└───────────┘ └───────────┘
ON time OFF time
- The data for the ON and OFF times are shown below. (NTSC)
| DATA (binary) | TIME (ms) | VBlanks |
|---|---|---|
| 0 0 0 0 | 0 | 0 |
| 0 0 0 1 | 166.9 | 10 |
| 0 0 1 0 | 333.8 | 20 |
| 0 0 1 1 | 500.5 | 30 |
| 0 1 0 0 | 667.5 | 40 |
| 0 1 0 1 | 843.4 | 50 |
| 0 1 1 0 | 1001.3 | 60 |
| 0 1 1 1 | 1168.2 | 70 |
| 1 0 0 0 | 1335.1 | 80 |
| 1 0 0 1 | 1501.9 | 90 |
| 1 0 1 0 | 1668.8 | 100 |
| 1 0 1 1 | 1835.7 | 110 |
| 1 1 0 0 | 2002.6 | 120 |
| 1 1 0 1 | 2169.5 | 130 |
| 1 1 1 0 | 2336.3 | 140 |
| 1 1 1 1 | 2503.2 | 150 |
Example of VRAM allocation in TEXT 2 mode
Pattern name table base address
00000H ┌──────────┐ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Name │ R#2 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 1 │
│ Table 0 │ └───┴───┴───┴───┴───┴───┴───┴───┘
00870H ├──────────┤ A16 A15 A14 A13 A12
│ │
00A00H ├ Color ─┤
│ Table 0 │ Color table base address
00B0EH ├──────────┤
00800H ├──────────┤ MSB 7 6 5 4 3 2 1 0 LSB
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Generator│ R#3 │ 0 │ 0 │ 1 │ 0 │ 1 │ 1 │ 1 │ 1 │
│ Table 0 │ └───┴───┴───┴───┴───┴───┴───┴───┘
01800H ├──────────┤ A13 A12 A11 A10 A9
│ Pattern │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Generator│ R#10 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │
│ Table 0 │ └───┴───┴───┴───┴───┴───┴───┴───┘
02000H ├──────────┤ A16 A15 A14
│ Pattern │
│ Name │
│ Table 1 │ Pattern generator table base address
02870H ├──────────┤
02A00H ├ Color ─┤ MSB 7 6 5 4 3 2 1 0 LSB
│ Table 1 │ ┌───┬───┬───┬───┬───┬───┬───┬───┐
02B0EH ├──────────┤ R#4 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 0 │
03000H ├──────────┤ └───┴───┴───┴───┴───┴───┴───┴───┘
│ Pattern │ A16 A15 A14 A13 A12 A11
│ Generator│
│ Table 0 │
│ │
03800H ├──────────┤
│ │
04000H ├──────────┤
. .
. . A maximum of 16 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
MULTICOLOR MODE
Characteristics
- Screen composition : 64 (w) x 48 (h) color blocks - Color blocks : Sixteen colors out of 512 colors - Sprite mode : Sprite mode 1 - VRAM area per screen : 4K bytes
Controls
- Color block color code : VRAM pattern generator table
- Color block location : VRAM pattern name table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table
VRAM sprite pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 0*│ 0*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 1*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in MULTICOLOR mode
** Indicates negative logic
2. Pattern Generator Table Settings
- The pattern generator table is an area that stores the colors of the color blocks.
- Each pattern is made up of four color blocks. These patterns are approximately 8 x 8 when the dots available for the screen display area is 256 x 192 dots.
◄──── 8 dots ───►
┌────────┬────────┐ ▲
│ │ │ │
│ A │ B │ │
│ │ │ │ For each block A, B, C,
├────────┼────────┤ 8 dots and D, sixteen colors may
│ │ │ │ be specified.
│ C │ D │ │
│ │ │ │
└────────┴────────┘ ▼
- In the MULTICOLOR mode, two bytes are used for each pattern, and each pattern includes four color blocks.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
│ Color code A │ Color code B │
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
│ Color code C │ Color code D │
└───┴───┴───┴───┴───┴───┴───┴───┘
- In the MULTICOLOR mode, for each pattern name, there are four corresponding color blocks, and according to the y-coordinate, the pattern names are automatically set.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┐ ┌───┬───┬───┬───┬───┬───┬───┬───┐
┌─ │ A │ B │ │ Color code A │ Color code B │ Pattern when
│ ├───┼───┤ ├───┼───┼───┼───┼───┼───┼───┼───┤ Y=0, 4, 8, 12, 16
│ │ C │ D │ │ Color code C │ Color code D │ or 20 is selected
│ └───┴───┘ └───┴───┴───┴───┴───┴───┴───┴───┘
│ ┌───┬───┐ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ │ E │ F │ │ Color code E │ Color code F │ Pattern when
│ ├───┼───┤ ├───┼───┼───┼───┼───┼───┼───┼───┤ Y=1, 5, 9, 13, 17
Pattern │ G │ H │ │ Color code G │ Color code H │ or 21 is selected
name └───┴───┘ └───┴───┴───┴───┴───┴───┴───┴───┘
#N ┌───┬───┐ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ │ I │ J │ │ Color code I │ Color code J │ Pattern when
│ ├───┼───┤ ├───┼───┼───┼───┼───┼───┼───┼───┤ Y=2, 6, 10, 14, 18
│ │ K │ L │ │ Color code K │ Color code L │ or 22 is selected
│ └───┴───┘ └───┴───┴───┴───┴───┴───┴───┴───┘
│ ┌───┬───┐ ┌───┬───┬───┬───┬───┬───┬───┬───┐
│ │ M │ N │ │ Color code M │ Color code N │ Pattern when
│ ├───┼───┤ ├───┼───┼───┼───┼───┼───┼───┼───┤ Y=3, 7, 11, 15, 19
└─ │ O │ P │ │ Color code O │ Color code P │ or 23 is selected
└───┴───┘ └───┴───┴───┴───┴───┴───┴───┴───┘
- Set the beginning (head) address of the pattern generator table in register R#4.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#4 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Pattern generator table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern generator table
│ │
├───────────────────┤ 0 Base address
│ Pattern name #0 │
│ (Eight bytes) │
├───────────────────┤ 8
│ Pattern name #1 │
│ (Eight bytes) │
├───────────────────┤ 16
. .
. .
. .
├───────────────────┤ 2040
│ Pattern name #255 │
│ (Eight bytes) │
├───────────────────┤ 2048
3. Pattern name table settings
- The pattern name table is composed of one byte for each screen pattern. Each byte specifies a unique pattern number.
Pattern name table
| 0 | 1 | 2 | 3 | ... | 31 | |
|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 2 | 3 | 31 | |
| 1 | 32 | 33 | 34 | 35 | 63 | |
| 22 | 704 | 705 | 735 | |||
| 23 | 736 | 737 | 767 |
- Set the beginning (head) address of the pattern name table in register R#2.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| R#2 | 0 | A16 | A15 | A14 | A13 | A12 | A11 | A10 | Pattern name table base address register |
Pattern name table
│ │
├─────────┤ Base address
│ ( 0, 0) │ 0
├─────────┤
│ ( 1, 0) │ 1
├─────────┤
│ ( 2, 0) │ 2
├─────────┤
¦ ¦ .
¦ ¦ .
¦ ¦ .
├─────────┤
│ (31, 0) │ 31
├─────────┤
│ ( 0, 1) │ 32
├─────────┤
¦ ¦ .
¦ ¦ .
¦ ¦ .
├─────────┤
│ (31,23) │ 767
├─────────┤
4. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop color
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
└───┴───┴───┴────────────────── Ignored
5. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 1.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│A9 │A8 │A7 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡ base address register
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in MULTICOLOR mode
00000H ┌──────────┐
│ Sprite │
│ Generator│
│ Table │
│ (1024 │
│ bytes) │
00400H ├──────────┤
│ Pattern │
│ Name │ .┌──────────┐ 00700H
│ Table │ . │ Sprite │
│ (768 │ . │ attribute│
│ bytes) │ . │ table │
00700H ├──────────┤. │ (128 │
│ │ │ bytes) │
│ │ ├──────────┤ 00780H
00800H ├──────────┤ │ │
│ │. │ │
│ │ . │ │
│ │ . │ │
│ │ . │ │
│ │ .└──────────┘ 00800H
│ │
│ Pattern │
00C00H │ Generator│
│ Table │
│ (2048 │
│ bytes) │
│ │
│ │
│ │
01000H ├──────────┤
. .
. . A maximum of 32 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
GRAPHIC 1 MODE
Characteristics
- Pattern size : 8 dots (w) x 8 dots (h) - Patterns : 256 types - Screen pattern count : 32 (w) x 24 (h) patterns - Pattern colors : 16 colors out of 512 colors (per screen) - Sprite mode : Sprite mode 1 - VRAM area per screen : 4K bytes
Controls
- Pattern font : VRAM pattern generator table
- Screen pattern location : VRAM pattern name table
- Pattern color codes 1 & 0: Can be specified as a group for each
8-pattern set, in the VRAM color table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 0*│ 0*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 1 mode
** Indicates negative logic
2. Pattern Generator Table Settings
- The pattern generator table is an area that stores the pattern fonts.
- Each pattern has a number from PN0 to PN255.
- The font for each pattern is constructed from 8 bytes.
- Set the beginning (head) address of the pattern generator table in register R#4.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#4 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Pattern generator table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern generator table
(X=1, O=0)
MSB 76543210 LSB
0 OOXXXOOO ─────┐
1 OXOOOXOO │
2 XOOOOOXO │
3 XOOOOOXO ├─── Pattern number 0
4 XXXXXXXO │
5 XOOOOOXO │
6 XOOOOOXO │
7 OOOOOOOO ─────┘
8 XXXXXXOO ─────┐
9 XOOOOOXO │
10 XOOOOOXO │
11 XXXXXXOO ├─── Pattern number 1
12 XOOOOOXO │
13 XOOOOOXO │
14 XXXXXXOO │
15 OOOOOOOO ─────┘
. . .
. . .
. . .
2040 XOXOXOXO ─────┐
2041 OXOXOXOX │
2042 XOXOXOXO │
2043 OXOXOXOX ├─── Pattern number 255
2044 XOXOXOXO │
2045 OXOXOXOX │
2046 XOXOXOXO │
2047 OXOXOXOX ─────┘
3. Pattern name table settings
- The pattern name table is composed of one byte for each screen pattern. Each byte specifies a unique pattern.
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│A14│A13│A12│A11│A10│ Pattern name table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern name table
│ │
├─────────┤ Base address
│ ( 0, 0) │ 0 0 1 2 3 . . 31 X
├─────────┤ ┌────┬────┬────┬────┬ ┬────┐
│ ( 1, 0) │ 1 0 │ 0│ 1│ 2│ 3│ . . │ 31│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
│ ( 2, 0) │ 2 1 │ 32│ 33│ 34│ 35│ . . │ 63│
├─────────┤ ├────┼────┼────┼────┼ ┼────┤
. . . . . . . . . . .
. . . . . . . . . . .
. . . ├────┼────┼ ──┼────┤
├─────────┤ 22 │ 704│ 705│ . . . . │ 735│
│ (31, 0) │ 31 ├────┼────┼ ──┼────┤
├─────────┤ 23 │ 736│ 737│ . . . . │ 767│
│ ( 0, 1) │ 32 └────┴────┴ ──┴────┘
├─────────┤ Y
. . .
. . . Screen display correspondence
. . .
├─────────┤
│ (31,21) │ 767 (byte)
├─────────┤
4. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop color
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
└───┴───┴───┴────────────────── Ignored
5. Color table settings
- The colors for pattern color 1 and pattern color 0 are set in groups of eight patterns.
- Set the beginning (head) address of the color table in registers R#3 and R#10.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#3 │A13│A12│A11│A10│A9 │A8 │A7 │A6 │ Color table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#10 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│A14│ base address register
└───┴───┴───┴───┴───┴───┴───┴───┘
Color table
┌───┬───┬───┬────────────────── Color code for part 1
│ │ │ │ ┌───┬───┬───┬── Color code for part 0
│ │ │ │ │ │ │ │
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐ Base address
0 │FC3│FC2│FC1│FC0│BC3│BC2│BC1│BC0│ Pattern Nos. 0 to 7
├───┼───┼───┼───┼───┼───┼───┼───┤
1 │FC3│FC2│FC1│FC0│BC3│BC2│BC1│BC0│ Pattern Nos. 8 to 15
├───┼───┼───┼───┼───┼───┼───┼───┤
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
├───┼───┼───┼───┼───┼───┼───┼───┤
31 │FC3│FC2│FC1│FC0│BC3│BC2│BC1│BC0│ Pattern Nos. 248 to 255
└───┴───┴───┴───┴───┴───┴───┴───┘
6. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 1.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│A9 │A8 │A7 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡ base address register
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in GRAPHIC 1 mode
00000H ┌──────────┐
│ Sprite │
│ Generator│
│ Table │
│ (1024 │
│ bytes) │
00400H ├──────────┤
│ Pattern │
│ Name │ .┌──────────┐ 00700H
│ Table │ . │ Sprite │
│ (768 │ . │ attribute│
│ bytes) │ . │ table │
00700H ├──────────┤. │ (128 │
│ │ │ bytes) │
│ │ ├──────────┤ 00780H
00800H ├──────────┤ │ Color │
│ │. │ table │
│ │ . ├(32 bytes)┤ 007A0H
│ │ . │ │
│ │ . │ │
│ │ .└──────────┘ 00800H
│ │
│ Pattern │
00C00H │ Generator│
│ Table │
│ (2048 │
│ bytes) │
│ │
│ │
│ │
01000H ├──────────┤
. .
. . A maximum of 32 pages may be allocated in
. . the same manner (using a 128K─byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
GRAPHIC 2 AND GRAPHIC 3 MODES
Characteristics
- Pattern size : 8 dots (w) x 8 dots (h)
- Patterns : 768 types
- Screen pattern count : 32 (w) x 24 (h) patterns
- Pattern colors : 16 colors out of 512 colors (per screen)
- Sprite modes : Sprite mode 1 (GRAPHIC 2)
: Sprite mode 2 (GRAPHIC 3)
- Vram area per screen : 16K bytes
* The GRAPHIC 2 and GRAPHIC 3 modes are identical except for the
sprite modes.
Controls
- Pattern font : VRAM pattern generator table
- Screen pattern location : VRAM pattern name table
- Pattern color codes 1 & 0: Can be specified as a group for each
: raster, in the VRAM color table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table.
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 0*│ 0*│ 0 │ Mode register 0
└───┴───┴───┴───┴───┴─┬─┴─┬─┴───┘
│ └────── 0, 1 for GRAPHIC 2 mode
└────────── 1, 0 for GRAPHIC 3 mode
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 2 mode or GRAPHIC 3 mode
** Indicates negative logic
All other bits are set accordingly.
2. Pattern Generator Table Settings
- The pattern generator table is an area that stores the pattern fonts.
- Each pattern has a number from PN0 to PN255; and since each group may have three members, 768 patterns may be specified.
- The font for each pattern is constructed from 8 bytes.
- Set the beginning (head) address of the pattern generator table in register R#4.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#4 │ 0 │ 0 │A16│A15│A14│A13│ 1 │ 1 │ Pattern generator table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
3. Color table settins
- The colors for pattern color 1 and pattern color 0 are set as a group of one raster.
- The color table corresponds to the pattern generator table on a one- to-one basis.
- Set the beginning (head) address of the color table in registers R#3 and R#10.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#3 │A13│ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ Color table address
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#10 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│A14│ register
└───┴───┴───┴───┴───┴───┴───┴───┘
4. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop color
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
└───┴───┴───┴────────────────── Ignored
Pattern generator table
(X=1, O=0)
MSB 76543210 LSB MSB 76543210 LSB
┌───── 0 OOXXXOOO OOOOOOOO
│ 1 OXOOOXOO OOOOOOOO
│ 2 XOOOOOXO OOOOOOOO
Pattern number 0 ───┤ 3 XOOOOOXO OOOOOOOO
│ 4 XXXXXXXO OOOOOOOO
│ 5 XOOOOOXO OOOOOOOO
│ 6 XOOOOOXO OOOOOOOO
└───── 7 OOOOOOOO OOOOOOOO
┌───── 8 XXXXXXOO OOOOOOOO
│ 9 XOOOOOXO OOOOOOOO
│ 10 XOOOOOXO OOOOOOOO
Pattern number 0 ───┤ 11 XXXXXXOO OOOOOOOO
│ 12 XOOOOOXO OOOOOOOO
│ 13 XOOOOOXO OOOOOOOO
│ 14 XXXXXXOO OOOOOOOO
└───── 15 OOOOOOOO OOOOOOOO
. . . .
. . . .
. . . .
┌─────2040 XOXOXOXO OOOOOOOO
│ 2041 OXOXOXOX OOOOOOOO
│ 2042 XOXOXOXO OOOOOOOO
Pattern number 255 ───┤ 2043 OXOXOXOX OOOOOOOO
│ 2044 XOXOXOXO OOOOOOOO
│ 2045 OXOXOXOX OOOOOOOO
│ 2046 XOXOXOXO OOOOOOOO
└─────2047 OXOXOXOX OOOOOOOO
│ ││ │
Color pattern 1 ───────────┴──┘│ │
Color pattern 0 ───────────────┴──┘
Pattern generator Color table
table
0 │ │ │ │
├─────────────┤ ├─────────────┤ ─┐
│ 256 patterns│ │ 256 colors │ │
│ for upper │ │ for upper │ │
│ third of │ │ third of │ │.
│ screen │ │ screen │ │ .. ┌─────────────────┐
│ (2048 bytes)│ │ (2048 bytes)│ │ ..│ Upper │
2048 ├─────────────┤ ├─────────────┤ ─┤ │ Third │
│ 256 patterns│ │ 256 colors │ │ ├─────────────────┤
│ for middle │ │ for middle │ │.....│ Middle │
│ third of │ │ third of │ │ │ Third │
│ screen │ │ screen │ │ ├─────────────────┤
│ (2048 bytes)│ │ (2048 bytes)│ │ │ Lower │
4096 ├─────────────┤ ├─────────────┤ ─┤ .│ Third │
│ 256 patterns│ │ 256 colors │ │ . └─────────────────┘
│ for lower │ │ for lower │ │ .. Display screen
│ third of │ │ third of │ │.
│ screen │ │ screen │ │
│ (2048 bytes)│ │ (2048 bytes)│ │
6144 ├─────────────┤ ├─────────────┤ ─┘
│ │ │ │
5. Pattern name table settings
- The pattern name table is composed of one byte for each screen pattern. Each byte specifies a unique pattern.
- The upper, middle, and lower parts of the screen can be used as three different parts, for a total of 768 patterns.
Pattern name table
┌──────────────────────────────────────────────────────┐
│ ( 0, 0) Pattern display area for upper (31, 0) │
│ third of screen (256 bytes) │
│ ( 0, 7) (31, 7) │
├──────────────────────────────────────────────────────┤
│ ( 0, 8) Pattern display area for middle (31, 8) │
│ third of screen (256 bytes) │
│ ( 0,15) (31,15) │
├──────────────────────────────────────────────────────┤
│ ( 0,16) Pattern display area for lower (31,16) │
│ third of screen (256 bytes) │
│ ( 0,23) (31,23) │
└──────────────────────────────────────────────────────┘
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│A14│A13│A12│A11│A10│ Pattern name table
└───┴───┴───┴───┴───┴───┴───┴───┘ base address register
Pattern name table
│ │
├─────────┤ Base address ──────────────┐
│ ( 0, 0) │ 0 │
├─────────┤ │
│ ( 1, 0) │ 1 ├── For upper third
├─────────┤ │ of screen
. . . │
├─────────┤ │
│ (31, 7) │ 255 │
├─────────┤ ────────────────────┤
│ ( 0, 8) │ 256 │
├─────────┤ ├── For middle third
. . . │ of screen
├─────────┤ │
│ (31,15) │ 511 │
├─────────┤ ────────────────────┤
│ ( 0,16) │ 512 │
├─────────┤ ├── For lower third
. . . │ of screen
├─────────┤ │
│ (31,23) │ 767 (byte) │
├─────────┤ ────────────────────┘
6. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites pertaining to GRAPHIC 2 MODE, see the section on SPRITE MODE 1, and for details about sprites pertaining to GRAPHIC 3 mode, see the section on SPRITE MODE 2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│A9 │A8 │A7 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡ base address register
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in GRAPHIC 2 mode
00000H ┌──────────┐
│ Pattern │
│ Generator│
│ Table │
│ Upper │
00800H ├──────────┤
│ Pattern │
│ Generator│
│ Table │
│ Middle │
01000H ├──────────┤
│ Pattern │ .┌──────────┐ 01C00H
│ Generator│ . │ Sprite │
│ Table │ . │ generator│
│ Lower │ . │ table │
01800H ├──────────┤. │ │
│ │ │ │
│ │ ├──────────┤ 01C00H
02000H ├──────────┤ │ Sprite │
│ Color │. │ attribute│
│ Table │ . │ table │
│ Upper │ . ├──────────┤ 01C80H
02800H ├──────────┤ . │ │
│ Color │ . │ │
│ Table │ .│ │
│ Middle │ └──────────┘ 02000H
├──────────┤
03000H │ Color │
│ Table │
│ Lower │
03800H ├──────────┤
│ Pattern │
│ Name │
│ Table │
03B00H ├──────────┤
│ Table │
04000H ├──────────┤
│ │
│ │
│ │
. .
. . A maximum of 8 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
Example of VRAM allocation in GRAPHIC 3 mode
00000H ┌──────────┐
│ Pattern │
│ Generator│
│ Table │
│ Upper │
00800H ├──────────┤
│ Pattern │
│ Generator│
│ Table │
│ Middle │
01000H ├──────────┤
│ Pattern │ .┌──────────┐ 01C00H
│ Generator│ . │ Sprite │
│ Table │ . │ generator│
│ Lower │ . │ table │
01800H ├──────────┤. │ │
│ │ │ │
│ │ ├──────────┤ 01C00H
02000H ├──────────┤ │ Sprite │
│ Color │. │ color │
│ Table │. │ table │
│ Upper │ . ├──────────┤ 01E00H
02800H ├──────────┤ . │ Sprite │
│ Color │ . │ attribute│
│ Table │ . │ table │
│ Middle │ . ├──────────┤ 01E80H
├──────────┤ . │ │
03000H │ Color │ .│ │
│ Table │ .└──────────┘ 02000H
│ Lower │
03800H ├──────────┤
│ Pattern │
│ Name │
│ Table │
03B00H ├──────────┤
│ Table │
04000H ├──────────┤
│ │
│ │
│ │
. .
. . A maximum of 8 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
GRAPHIC 4 MODE
Characteristics
- Bit-mapped Graphics Mode
- Screen size : 256 (w) x 212 (h) dots
: 256 (w) x 192 (h) dots
- Screen colors : 16 colors out of 512 colors (per screen)
- Sprite mode : Sprite mode 2
- VRAM area per screen : 32K bytes
Controls
- Graphics : VRAM pattern name table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 0*│ 1*│ 1*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 4 mode
** Indicates negative logic
In GRAPHIC 4 mode, if LN is set to 1, the screen height is 212 dots,
and if LN is set to 0, the screen height is 192 dots.
All other bits are set accordingly.
2. Pattern name table settings
- The pattern name table is composed of one byte for every two dots on the screen. A color can be assigned for each dot from a collection of 16 colors out of 512 colors.
┌────► X
│ ┌───────┬───────┬..................┬─────────┬─────────┐
│ │(0, 0)│(1, 0)│ │(254, 0)│(255, 0)│
▼ ├───────┼───────┘ └─────────┼─────────┤
Y │(0, 1)│ │(255, 1)│
├───────┘ ┌─────────┐ └─────────┤
│ │ (X,Y) │ │
. └─────────┘ .
. .
. .
│ │
│ │
│ │
│ │
├───────┐ ┌─────────┤
│(0,191)│ │(255,191)│
└───────┴────────────────────────────────────┴─────────┘ LN = 0
│ │
├───────┐ ┌─────────┤
│(0,211)│ │(255,211)│
└───────┴────────────────────────────────────┴─────────┘ LN = 1
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│ 1 │ 1 │ 1 │ 1 │ 1 │ Pattern name table
└───┴─┬─┴─┬─┴───┴───┴───┴───┴───┘ base address register
│ │
└───┴────────────────────── These two bits specify
the page to display
Pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
┌────┬───┬───┬───┬───┬───┬───┬───┐
1 │ ( 0, 0) │ ( 1, 0) │ Base address
├────┼───┼───┼───┼───┼───┼───┼───┤
2 │ ( 2, 0) │ ( 3, 0) │ Set the color code for each
├────┴───┴───┴───┴───┴───┴───┴───┤ dot in this table
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
127 │ (254, 0) │ (255, 0) │
├────┼───┼───┼───┼───┼───┼───┼───┤
128 │ ( 0, 1) │ ( 1, 1) │
├────┴───┴───┴───┴───┴───┴───┴───┤
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
27134 │ (252,211) │ (253,211) │
├────┼───┼───┼───┼───┼───┼───┼───┤
27135 │ (254,211) │ (255,211) │
└────┴───┴───┴───┴───┴───┴───┴───┘
3. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ color register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
│ │ │ │ code
└───┴───┴───┴────────────────── Ignored
4. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│ 1 │ 1 │ 1 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│ base address register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in GRAPHIC 4 mode
00000H ┌──────────┐
│ │
│ │
│ │
02000H │ Pattern │
│ name │
│ table │
│ │
04000H │ │
│ │
│ │
│ 192 lines│
06000H ├──────────┤
│ │ .┌──────────┐ 07000H
│ │ . │ Sprite │
│ 212 lines│ .. │ generator│
06A00H ├──────────┤. │ table │
│ │ │ (2048 │
07000H ├──────────┤ │ bytes) │
│ │ ├──────────┤ 07800H
│ │ │ Sprite │
│ │ │ color │
│ │ │ table │
│ │ │ (512 │
│ │ │ bytes) │
│ │ ├──────────┤ 07A00H
│ │ │ Sprite │
│ │ │ attribute│
│ │ │ table │
08000H ├──────────┤. │ (128 │
. . . │ bytes │
. . . ├──────────┤ 07A80H
. . . │ │
. . .└──────────┘ 08000H
. .
│ │
│ │ A maximum of 4 pages may be allocated in
1FFFFH └──────────┘ the same manner (using a 128K-byte VRAM).
GRAPHIC 5 MODE
Characteristics
- Bit-mapped Graphics Mode
- Screen size : 512 (w) x 212 (h) dots
: 512 (w) x 192 (h) dots
- Screen colors : 4 colors out of 512 colors (per screen)
- Sprite mode : Sprite mode 2
- VRAM area per screen : 32K bytes
Controls
- Graphics : VRAM pattern name table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 1*│ 0*│ 0*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 4 mode
** Indicates negative logic
In GRAPHIC 5 mode, if LN is set to 1, the screen height is 212 dots,
and if LN is set to 0, the screen height is 192 dots.
All other bits are set accordingly.
2. Pattern name table settings
- The pattern name table is composed of one byte for every four dots on the screen. A color can be assigned for each dot from a selection of 4 colors out of 512 colors.
┌────► X
│ ┌───────┬───────┬..................┬─────────┬─────────┐
│ │(0, 0)│(1, 0)│ │(510, 0)│(511, 0)│
▼ ├───────┼───────┘ └─────────┼─────────┤
Y │(0, 1)│ │(511, 1)│
├───────┘ ┌─────────┐ └─────────┤
│ │ (X,Y) │ │
. └─────────┘ .
. .
. .
│ │
│ │
│ │
│ │
├───────┐ ┌─────────┤
│(0,191)│ │(511,191)│
└───────┴────────────────────────────────────┴─────────┘ LN = 0
│ │
├───────┐ ┌─────────┤
│(0,211)│ │(511,211)│
└───────┴────────────────────────────────────┴─────────┘ LN = 1
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │A16│A15│ 1 │ 1 │ 1 │ 1 │ 1 │ Pattern name table
└───┴─┬─┴─┬─┴───┴───┴───┴───┴───┘ base address register
│ │
└───┴────────────────────── These two bits specify
the page to display
Pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
┌────┬───┬───┬───┬───┬───┬───┬───┐
1 │ ( 0, 0)│( 1, 0)│( 2, 0)│( 3, 0)│ Base address
├────┼───┼───┼───┼───┼───┼───┼───┤
2 │ ( 4, 0)│( 5, 0)│( 6, 0)│( 7, 0)│ Set the color code for each
├────┴───┴───┴───┴───┴───┴───┴───┤ dot in this table
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
127 │ (508,0)│(509,0)│(510,0)│(511,0)│
├────┼───┼───┼───┼───┼───┼───┼───┤
128 │ ( 0, 1)│( 1, 1)│( 2, 1)│( 3, 1)│
├────┴───┴───┴───┴───┴───┴───┴───┤
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
27135 │ │ │ │ │ │ (511,211)│
└────┴───┴───┴───┴───┴───┴───┴───┘
3. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ color register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
│ │ │ │ code
└───┴───┴───┴────────────────── Ignored
4. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│ 1 │ 1 │ 1 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│ base address register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
5. Hardware tiling function
- In GRAPHIC 5 mode, a hardware tiling function processes the sprite and background colors. For these colors, you can specify four bits; however, of these four bits, the higher-order two bits specify the color code of the even dots, and the lower-order two bits specify the color code of the odd dots of the x-coordinage (0 to 511).
- In GRAPHIC 5 mode, the size of one dot of a sprite is approximately twice that of a graphics dot; however, when this tiling function is used, one dot of a sprite may be displayed in two colors.
- The even and odd dots of the background colors may also be specified in the same manner.
┌──────── Even dots (0, 2, . . . 510)
│ ┌─── Odd dots (1, 3, . . . 511)
│ │
┌┴──┬─┴─┐
│ │ │ Two graphics dots
└───┴───┘
┌───────┐
│ │ A sprite dot
└───────┘
┌───┬───┐
│ │XXX│
└┬──┴┬──┘
│ │
├─┐ ├─┐
│ │ │ │
┌┴┬┴┬┴┬┴┐
MSB │/│/│/│/│ LSB Bit specifying sprite colors (4 bits)
└─┴─┴─┴─┘
Example of VRAM allocation in GRAPHIC 5 mode
00000H ┌──────────┐
│ │
│ Pattern │
│ name │
02000H │ table │
│ │
│ │
│ │
04000H │ │
│ │
│ │
│ 192 lines│
06000H ├──────────┤
│ │ .┌──────────┐ 07000H
│ │ . │ Sprite │
│ 212 lines│ .. │ generator│
06A00H ├──────────┤. │ table │
│ │ │ (2048 │
07000H ├──────────┤ │ bytes) │
│ │ ├──────────┤ 07800H
│ │ │ Sprite │
│ │ │ color │
│ │ │ table │
│ │ │ (512 │
│ │ │ bytes) │
│ │ ├──────────┤ 07A00H
│ │ │ Sprite │
│ │ │ attribute│
│ │ │ table │
│ │ │ (128 │
│ │ │ bytes │
│ │ ├──────────┤ 07A80H
│ │ │ │
08000H ├──────────┤.....└──────────┘ 08000H
. .
. .
. . A maximum of 4 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
GRAPHIC 6 MODE
Characteristics
- Bit-mapped Graphics Mode
- Screen size : 512 (w) x 212 (h) dots
: 512 (w) x 192 (h) dots
- Screen colors : 16 colors out of 512 colors (per screen)
- Sprite mode : Sprite mode 2
- VRAM area per screen : 128K bytes (Two screens)
* To use this mode, the VRAM must have 128K bytes.
Controls
- Graphics : VRAM pattern name table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 1*│ 0*│ 1*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 4 mode
** Indicates negative logic
In GRAPHIC 6 mode, if LN is set to 1, the screen height is 212 dots,
and if LN is set to 0, the screen height is 192 dots.
All other bits are set accordingly.
2. Pattern name table settings
- The pattern name table is composed of one byte for every two dots on the screen. A color can be assigned for each dot from a selection of 16 colors out of 512 colors.
┌────► X
│ ┌───────┬───────┬..................┬─────────┬─────────┐
│ │(0, 0)│(1, 0)│ │(510, 0)│(511, 0)│
▼ ├───────┼───────┘ └─────────┼─────────┤
Y │(0, 1)│ │(511, 1)│
├───────┘ ┌─────────┐ └─────────┤
│ │ (X,Y) │ │
. └─────────┘ .
. .
. .
│ │
│ │
│ │
│ │
├───────┐ ┌─────────┤
│(0,191)│ │(511,191)│
└───────┴────────────────────────────────────┴─────────┘ LN = 0
│ │
├───────┐ ┌─────────┤
│(0,211)│ │(511,211)│
└───────┴────────────────────────────────────┴─────────┘ LN = 1
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │ 0 │A16│ 1 │ 1 │ 1 │ 1 │ 1 │ Pattern name table
└───┴───┴─┬─┴───┴───┴───┴───┴───┘ base address register
│
└─────── Specifies the page to display (In G6 and
G7 modes, the position of A16 differs).
Pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
┌────┬───┬───┬───┬───┬───┬───┬───┐
1 │ ( 0, 0) │ ( 1, 0) │ Base address
├────┼───┼───┼───┼───┼───┼───┼───┤
2 │ ( 2, 0) │ ( 3, 0) │ Set the color code for each
├────┴───┴───┴───┴───┴───┴───┴───┤ dot in this table
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
255 │ (510, 0) │ (511, 0) │
├────┼───┼───┼───┼───┼───┼───┼───┤
256 │ ( 0, 1) │ ( 1, 1) │
├────┴───┴───┴───┴───┴───┴───┴───┤
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
54270 │ (508,211) │ (509,211) │
├────┼───┼───┼───┼───┼───┼───┼───┤
54271 │ (510,211) │ (511,211) │
└────┴───┴───┴───┴───┴───┴───┴───┘
3. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ color register
│ │ │ │ │ │ │ │
│ │ │ │ └───┴───┴───┴── Specifies backdrop color
│ │ │ │ code
└───┴───┴───┴────────────────── Ignored
4. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│ 1 │ 1 │ 1 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│ base address register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in GRAPHIC 6 mode
00000H ┌──────────┐
│ │
│ Pattern │
│ Name │
│ table │
│ │
│ │
│ │
04000H │ │
│ │
│ │
│ │
│ │
│ │
08000H │ │
│ │
│ │ ┌──────────┐ 0F000H
│ │ .│ Sprite │
│ 192 line │ .│ generator│
0C000H ├──────────┤ .│ table │
│ 212 line │ . │ (2048 │
0D400H ├──────────┤ . │ bytes) │
│ │ . ├──────────┤ 0F800H
│ │ . │ Sprite │
│ │ . │ color │
│ │ . │ table │
│ │ . │ (512 │
│ │ . │ bytes) │
│ │ . ├──────────┤ 0FA00H
│ │ . │ Sprite │
│ │ . │ attribute│
│ │. │ table │
│ │. │ (128 │
│ │. │ bytes │
0F000H ├──────────┤ ├──────────┤ 0FA80H
│ │ │ │
08000H ├──────────┤.....└──────────┘ 10000H
. .
. .
. . A maximum of 2 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
GRAPHIC 7 MODE
Characteristics
- Bit-mapped Graphics Mode
- Screen size : 256 (w) x 212 (h) dots
: 256 (w) x 192 (h) dots
- Screen colors : 256 colors (per screen)
- Sprite mode : Sprite mode 2
- VRAM area per screen : 128K bytes (Two screens)
* To use this mode, the VRAM must have 128K bytes.
Controls
- Graphics : VRAM pattern name table
- Background color code : Low-order four bits of R#7
- Sprites : VRAM sprite attribute table, VRAM sprite
pattern table
Initial Settings
1. Mode and Register Settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#0 │ 0 │DG │IE2│IE1│ 1*│ 1*│ 1*│ 0 │ Mode register 0
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#1 │ 0 │BL │IE0│ 0*│ 0*│ 0 │SI │MAG│ Mode register 1
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#8 │MS │LP │TP │CB │VR │ 0 │SPD│BW │ Mode register 2
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#9 │LN │ 0 │S1 │S0 │IL │EO **NT│DC │ Mode register 3
└───┴───┴───┴───┴───┴───┴───┴───┘
* Examples of settings in GRAPHIC 4 mode
** Indicates negative logic
In GRAPHIC 7 mode, if LN is set to 1, the screen height is 212 dots,
and if LN is set to 0, the screen height is 192 dots.
All other bits are set accordingly.
2. Pattern name table settings
- The pattern name table is composed of one byte for every dot on the screen. A color can be assigned for each dot from a selection of 256 colors.
┌────► X
│ ┌───────┬───────┬..................┬─────────┬─────────┐
│ │(0, 0)│(1, 0)│ │(254, 0)│(255, 0)│
▼ ├───────┼───────┘ └─────────┼─────────┤
Y │(0, 1)│ │(255, 1)│
├───────┘ ┌─────────┐ └─────────┤
│ │ (X,Y) │ │
. └─────────┘ .
. .
. .
│ │
│ │
│ │
│ │
├───────┐ ┌─────────┤
│(0,191)│ │(255,191)│
└───────┴────────────────────────────────────┴─────────┘ LN = 0
│ │
├───────┐ ┌─────────┤
│(0,211)│ │(255,211)│
└───────┴────────────────────────────────────┴─────────┘ LN = 1
- Set the beginning (head) address of the pattern name table in register R#2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#2 │ 0 │ 0 │A16│ 1 │ 1 │ 1 │ 1 │ 1 │ Pattern name table
└───┴───┴─┬─┴───┴───┴───┴───┴───┘ base address register
│
└──── Specifies the page to display; in the G6
and G7 modes only, the location of the A16
bit differs.
Pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
┌────┬───┬───┬───┬───┬───┬───┬───┐
1 │ │ │ ( 0, 0) │ │ │ Base address
├────┼───┼───┼───┼───┼───┼───┼───┤
2 │ │ │ ( 1, 0) │ │ │ Set the color code for each
├────┴───┴───┴───┴───┴───┴───┴───┤ dot in this table
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
│ GREEN │ RED │ BLUE │
├────┴───┴───┴───┴───┴───┴───┴───┤
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
255 │ │ │ ( 255, 0) │ │ │
├────┼───┼───┼───┼───┼───┼───┼───┤
256 │ │ │ ( 0, 1) │ │ │
├────┴───┴───┴───┴───┴───┴───┴───┤
. .
. .
. .
├────┬───┬───┬───┬───┬───┬───┬───┤
54270 │ │ │ ( 254, 211) │ │ │
├────┼───┼───┼───┼───┼───┼───┼───┤
54271 │ │ │ ( 255, 211) │ │ │
└────┴───┴───┴───┴───┴───┴───┴───┘
3. Color register settings
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#7 │TC3│TC2│TC1│TC0│BD3│BD2│BD1│BD0│ Text color/Back drop
└─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┘ color register
│ │ │ │ │ │ │ │
└───┴───┴───┴───┴───┴───┴───┴── Specifies backdrop color
code
4. Sprite settings
- Set the beginning (head) address of the sprite attribute table in registers R#5 and R#11; and set the beginning (head) address of the sprite pattern generator table in register R#6. For details about sprites, see the section on SPRITE MODE 2.
MSB 7 6 5 4 3 2 1 0 LSB
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#5 │A14│A13│A12│A11│A10│ 1 │ 1 │ 1 │ Sprite attribute table
╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡
R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│ base address register
└───┴───┴───┴───┴───┴───┴───┴───┘
┌───┬───┬───┬───┬───┬───┬───┬───┐
R#6 │ 0 │ 0 │A16│A15│A14│A13│A12│A11│ Sprite pattern generator
└───┴───┴───┴───┴───┴───┴───┴───┘ table base address
register
Example of VRAM allocation in GRAPHIC 7 mode
00000H ┌──────────┐
│ │
│ Pattern │
│ Name │
│ table │
│ │
│ │
│ │
04000H │ │
│ │
│ │
│ │
│ │
│ │
08000H │ │
│ │
│ │ ┌──────────┐ 0F000H
│ │ .│ Sprite │
│ 192 line │ .│ generator│
0C000H ├──────────┤ .│ table │
│ 212 line │ . │ (2048 │
0D400H ├──────────┤ . │ bytes) │
│ │ . ├──────────┤ 0F800H
│ │ . │ Sprite │
│ │ . │ color │
│ │ . │ table │
│ │ . │ (512 │
│ │ . │ bytes) │
│ │ . ├──────────┤ 0FA00H
│ │ . │ Sprite │
│ │ . │ attribute│
│ │. │ table │
│ │. │ (128 │
│ │. │ bytes │
0F000H ├──────────┤ ├──────────┤ 0FA80H
│ │ │ │
08000H ├──────────┤.....└──────────┘ 10000H
. .
. .
. . A maximum of 2 pages may be allocated in
. . the same manner (using a 128K-byte VRAM).
. .
│ │
│ │
1FFFFH └──────────┘
COMMANDS
1. Types of Commands
It is very easy to use MSX-VIDEO commands to perform functions such as LINE and PSET for use with graphics, and for transferring parts of the screen.
| Command Name | Destination | Source | Late | Mnemonic | CM3 | CM2 | CM3 | CM0 |
|---|---|---|---|---|---|---|---|---|
| High-speed move | VRAM | CPU | Byte | HMMC | 1 | 1 | 1 | 1 |
| VRAM | VRAM | Byte | YMMM | 1 | 1 | 1 | 0 | |
| VRAM | VRAM | Byte | HMMM | 1 | 1 | 0 | 1 | |
| VRAM | VDP | Byte | HMMV | 1 | 1 | 0 | 0 | |
| Logical move | VRAM | CPU | Dot | LMMC | 1 | 0 | 1 | 1 |
| CPU | VRAM | Dot | LMCM | 1 | 0 | 1 | 0 | |
| VRAM | VRAM | Dot | LMMM | 1 | 0 | 0 | 1 | |
| VRAM | VDP | Dot | LMMV | 1 | 0 | 0 | 0 | |
| Line | VRAM | VDP | Dot | LINE | 0 | 1 | 1 | 1 |
| Search | VRAM | VDP | Dot | SRCH | 0 | 1 | 1 | 0 |
| Pset | VRAM | VDP | Dot | PSET | 0 | 1 | 0 | 1 |
| Point | VDP | VRAM | Dot | POINT | 0 | 1 | 0 | 0 |
| Invalid | 0 | 0 | 1 | 1 | ||||
| Invalid | 0 | 0 | 1 | 0 | ||||
| Invalid | 0 | 0 | 0 | 1 | ||||
| Stop | 0 | 0 | 0 | 0 |
- Commands are executed in the MSX-VIDEO by writing the data into R#46 (the Command Register, hereafter abbreviated CMR), and setting bit 0 of status register S#2 (CE/Command Execute) to 1. Before this can be done, the necessary parameters must first have been set in registers R#32 to R#45.
- When the command execution is complete, CE is set to 0.
- To abort a command while it is being executed, execute a STOP.
- The results of command execution are only guaranteed during bit map mode (Graph4 to Graph7).
2. Page Concept
The parameters used for the MSX-VIDEO are all x-y coordinates. In other words, the internal command processor of the MSX-VIDEO accesses the entire VRAM area as x-y coordinates of the display mode.
When a screen is to be displayed, 212 lines of the same page are displayed (selected by R#23). To select the page to be displayed, use R#2.
When a command is being executed, the contents of the display screen are ignored.
The display modes and their relationships to the coordinates are shown in the table below.
| GRAPH 4 | Address | GRAPH 5 |
|---|---|---|
┌──────────────────────────┐ │(0,0) (255,0)│ │ Page 0 │ │(0,255) (255,255)│ ├──────────────────────────┤ │(0,256) (255,256)│ │ Page 1 │ │(0,511) (255,511)│ ├──────────────────────────┤ │(0,512) (255,512)│ │ Page 2 │ │(0,767) (255,767)│ ├──────────────────────────┤ │(0,768) (255,768)│ │ Page 3 │ │(0,1023) (255,1023)│ └──────────────────────────┘ |
00000H │ │ │ 08000H │ │ │ 10000H │ │ │ 18000H │ │ │ 1FFFFH |
┌──────────────────────────┐ │(0,0) (511,0)│ │ Page 0 │ │(0,255) (511,255)│ ├──────────────────────────┤ │(0,256) (511,256)│ │ Page 1 │ │(0,511) (511,511)│ ├──────────────────────────┤ │(0,512) (511,512)│ │ Page 2 │ │(0,767) (511,767)│ ├──────────────────────────┤ │(0,768) (511,768)│ │ Page 3 │ │(0,1023) (511,1023)│ └──────────────────────────┘ |
| GRAPH 7 | Address | GRAPH 6 |
|---|---|---|
┌──────────────────────────┐ │(0,0) (255,0)│ │ Page 0 │ │(0,255) (255,255)│ ├──────────────────────────┤ │(0,256) (255,256)│ │ Page 1 │ │(0,511) (255,511)│ └──────────────────────────┘ |
00000H │ │ │ 10000H │ │ │ 1FFFFH |
┌──────────────────────────┐ │(0,0) (511,0)│ │ Page 0 │ │(0,255) (511,255)│ ├──────────────────────────┤ │(0,256) (511,256)│ │ Page 1 │ │(0,511) (511,511)│ └──────────────────────────┘ |
3. Logical Operations
When the LINE, PSET and LOGICAL MOVE commands are executed on the MSX-VIDEO, the operations may be performed on the color on the screen. To do logical operations on the MSX-VIDEO, write the lower four bits of R#46 (Command register) simultaneously when you specify the command.
Summary of Logical Operations
| Name | Operation | LO3 | LO2 | LO1 | LO0 |
|---|---|---|---|---|---|
| IMP | DC=SC | 0 | 0 | 0 | 0 |
| AND | SC*DC | 0 | 0 | 0 | 1 |
| OR | SC+DC | 0 | 0 | 1 | 0 |
| EOR | 0 | 0 | 1 | 1 | |
| NOT | DC= |
0 | 1 | 0 | 0 |
| --- | 0 | 1 | 0 | 1 | |
| --- | 0 | 1 | 1 | 0 | |
| --- | 0 | 1 | 1 | 1 | |
| TIMP | if SC=0 then DC=DC else DC=SC | 1 | 0 | 0 | 0 |
| TAND | if SC=0 then DC=DC else SC*DC | 1 | 0 | 0 | 1 |
| TOR | if SC=0 then DC=DC else SC+DC | 1 | 0 | 1 | 0 |
| TEOR | if SC=0 then DC=DC else |
1 | 0 | 1 | 1 |
| TNOT | if SC=0 then DC=DC else DC= |
1 | 1 | 0 | 0 |
| --- | 1 | 1 | 0 | 1 | |
| --- | 1 | 1 | 1 | 0 | |
| --- | 1 | 1 | 1 | 1 |
* SC = Source Color code
* DC = Destination Color code
* EOR = Exclusive OR
4. Explanation of Commands
4.1 HMMC (High-speed move CPU to VRAM)
The HMMC command transfers data from the CPU to the Video or expansion RAM in a specified rectangular area (in x-y coordinates) via the MSX-VIDEO.
Since the data to be transferred is done in units of one byte, there is a limitation, according to the display mode, on the value for x.
4.1.1 HMMC Execution Order
-
First, set the necessary parameters in the command register of the MSX-VIDEO.
MXD: Select destination memory
0: Video RAM
1: Expansion RAMDX: Basic x-coordinate of destination (0 to 511) *1 DY: Basic y-coordinate of destination (0 to 1023) NX: Dots to move in x-direction (0 to 511) *1 NY: Dots to move in x-direction (0 to 1023) *1 Note that in the G4 and G6 modes, the lower one bit, and in the G5 mode, the lower two bits are lost.
DIX: Direction for NX from x-coordinate of destination
0: Right
1: LeftDIY: Direction for NY from y-coordinate of destination
0: Down
1: UpCLR: (R#44: Color register)
First byte of data to be transferred After you specify the above data, execute the command by writing 1 1 1 1 0 0 0 0 B into the CMR (R#46: Command register).
While checking TR and CE in Status Register #2, send the second byte and all bytes following into the CLR register.
4.1.2 Setting up the HMMC register
…
5. Speeding up the processing of commands
The processing of commands can be speeded up by the following two methods.
5.1 Inhibit the display of sprites
If bit 1 of Register R#8 (SPD) is set to 1, processing for sprites can be used for commands instead; and therefore the command execution is faster.
5.2 Inhibit the screen display
If bit 6 of Register R#1 (BL) is set to 1, processing for the screen can be used for commands instead; and therefore the command execution is faster.
6. Conditions of registers after command execution
After commands on the MSX-VIDEO are executed, the conditions of the registers will be as listed in the following table.
| SX | SY | DX | DY | NX | NY | CLR | CMR H | CMR L | ARG | |
|---|---|---|---|---|---|---|---|---|---|---|
| HMMC | - | - | - | * | - | # | - | 0 | - | - |
| YMMM | - | * | - | * | - | # | - | 0 | - | - |
| HMMM | - | * | - | * | - | # | - | 0 | - | - |
| HMMV | - | - | - | * | - | # | - | 0 | - | - |
| LMMC | - | - | - | * | - | # | - | 0 | - | - |
| LMCM | - | * | - | - | - | # | * | 0 | - | - |
| LMMM | - | * | - | * | - | # | - | 0 | - | - |
| LMMV | - | - | - | * | - | # | - | 0 | - | - |
| LINE | - | - | - | * | - | - | - | 0 | - | - |
| SRCH | - | - | - | - | - | - | - | 0 | - | - |
| PSET | - | - | - | - | - | - | - | 0 | - | - |
| POINT | - | - | - | - | - | - | * | 0 | - | - |
- Unchanged
* Coordinate at command end (SY*, DY*) or color code
# The count (NYB) when the end of the screen was detected
Note: The values for SY*, DY* and NYB are the dots, as substituted for N in the equations below.
SY* = SY + N DY* = DY + N (DIY = 0) SY* = SY - N DY* = DY - N (DIY = 1) NYB = NY - N
( “LINE” command ==> if MAJ=0 then N=N-1 )
SPRITES
The MSX-VIDEO can be used to display 32 sprites. The size of the sprites are 8 x 8 or 16 x 16 dots. The size in the horizontal direction of a sprite is 1/256 of the screen. The sprites may be placed anywhere on the screen.
Since the sprites are handled in a conceptually independent screen, they do not affect the data within other screens.
(Sprite Screen)
(0,255)* (255,255)*
┌────────────────────────────────────────────────┐
│ (X,Y) ▲ │
│ ┌────┐ │ │
│ │ │ │ │
│ └────┘ │ │
│ Sprite │ ┌─┴──┐
│ │ │ │
│ CRT area displayed └────┘
│ │ Sprite
│ │ │
│ │ │
│ │ │
(0,191)│ ┌────┐ ▼ │ (255,191)
or ├──────────┤ ├────────────────────────────────┤ or
(0,211)│ └----┘ ▲ │ (255,211)
│ Sprite │ │
│ CRT area undisplayed │
│ │ │
│ ▼ │
└────────────────────────────────────────────────┘
(0,254) (255,254)
* The y-coordinate of the upper edge of a sprite is 255.
The MSX-VIDEO has two sprite display modes. The sprite display mode is automatically selected according to the screen display mode.
| SPRITE MODE 1: | GRAPHIC 1, GRAPHIC 2, MULTICOLOR |
| SPRITE MODE 1: | GRAPHIC 3, GRAPHIC 4, GRAPHIC 5, GRAPHIC 6, GRAPHIC 7 |
1. SPRITE MODE 1 (G1, G2, MC)
1.1 Characteristics of SPRITE MODE 1
In SPRITE MODE 1, there are 32 sprites, numbered #0 to #31. The sprites assigned the lower numbers have a higher priority. On a single CRT horizontal line, up to 4 sprites with the highest priority are displayed, and the overlapping portions of sprites with lower priorities are not displayed.
┌────────────────────────────────────────────────┐
│ │
│ ┌──┐ ┌──┐ ┌──┐ │
│ │#1│ ┌──┐ ┌──┐ │#4│ :#5: .... │
│ └──┘ │#2│ │#3│ └──┘ :..: :#6: │
│ └──┘ └──┘ └──┘ │
│ │
│ │
│ │
│ │
│ │
│ │
└────────────────────────────────────────────────┘
When two sprites collide (their pattern color 1 portions have overlapped), this condition may be detected since bit 5 of status register S#0 is set to 1.
In addition, if there are five or more sprites on one horizontal line, bit 6 of status register S#0 will be set to 1, and the lower-order five bits will be set to the number of the fifth sprite.
1.2 SPRITE MODE 1 display (G1, G2, MC)
To display sprites, use the following controls.
-
Sprite size R#1 bit 1
SI = 1: 16 x 16 dots
SI = 0: 8 x 8 dots -
Sprite magnification R#1 bit 0
MAG = 1: Double-size
MAG = 0: Normal - Setting the sprite pattern generator table
Set the sprite’s pattern in the Sprite Pattern Generator Table of the VRAM (#0 to #255). - Setting the sprite attribute table
Set the sprite’s attributes (its coordinates, pattern number, and colors) in the Sprite Attribute Table of the VRAM (#0 to #31).
1.3 Sprite Attribute Table (G1, G2, MC)
The Sprite Attribute Table is an area in the VRAM that contains the display (x- and y-) coordinates, colors, and pattern numbers of the 32 sprites. Each sprite has four bytes of attribute data.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Y-coordinate (0 to 255) | ┐ Sprite attribute table base address | ||||||||
| X-coordinate (0 to 255) | │ | ||||||||
| Pattern number (0 to 255) | ├── Attribute area for sprite #0 | ||||||||
| EC | 0 | 0 | 0 | Color code | ┘ | ||||
| ┬── Attribute area for sprite #1 | |||||||||
| ┤ | |||||||||
| ┆ ├── Attribute area for sprite #1 |
|||||||||
| ┘ | |||||||||
-
Y-coordinate (0 to 255)
Specify the y-coordinate of the sprite
If the value for the sprite’s y-coordinate is set to 208, all sprites with lower priority will not be displayed. For example, if sprite #10’s y-coordinate is set to 208, sprites #10 to #31 will not be displayed. -
X-coordinate (0 to 255)
Specify the x-coordinate of the sprite. -
Pattern number (0 to 255)
Specify the sprite pattern number in the sprite pattern generator table. If the size of the sprite is 16 x 16, there will be four sprite pattern numbers corresponding to one sprite. In this case, you may specify any one of the four sprite pattern numbers.In the above manner, if all sprites are 8 x 8, there will be 256 possible patterns; however, if all sprites are 16 x 16, there will be 64 possible patterns.
-
Color code (0 to 15)
Specify the color code for pattern color 1. The color code for pattern color 0 will be transparent. -
EC (Early clock)
When this bit is set to 1, the 32 dots of the sprite are shifted to the left. In other words, when this function is used, the sprite is moved to the left, one dot at a time, from the left edge of the screen.│ │ │ │ Left edge of CRT │◄── 32 dots ──►│ │ │ │ ┌───┼───┐ │ │ │ │ Sprite │ └───┼───┘ │ │
1.4 Sprite Pattern Generator Table (G1, G2, MC)
The Sprite Pattern Generator Table is an area in the VRAM to specify the sprite patterns (its appearance). The beginning (head) address of this area must be specified in register R#6 (Sprite Pattern Generator Table Base Address Register).
The pattern for each sprite must be written in this area. Eight bytes are used for each pattern, for a total of 256 patterns. Each of the 256 patterns are assigned a sprite pattern number from #0 to #255; if the sprite size is 8 x 8 dots, each sprite has one pattern and if the sprite size is 16 x 16 dots, each sprite has four patterns.
VRAM
│ ◄── 1 byte ──► │
├────────────────┤ ─┐ Sprite Pattern Generator Table
│ │ │ Base Address
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ├── Pattern #0
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ─┤
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ├── Pattern #1
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ─┤
¦ . ¦ │
¦ . ¦
│ │ Pattern #255 (Maximum)
├────────────────┤
│ │
1.5 Example of Data Setting for Sprite Pattern Generator Table (G1, G2, MC)
1.5 Example of Data Setting for Sprite Pattern (X=1, O=0) N=0, 1, . . . , 255
(Pattern Name Table Base Address for N=0)
MSB LSB
76543210 Address Example of 16 x 16 Sprite
OOOOOOOX 8N
OOOOOXXX 8N+1 OOOOOOOXXOOOOOOO
OOOXXXXX . OOOOOXXXXXXOOOOO
OOOOXXXO . Pattern number 0 OOOXXXXXXXXXXOOO
OOOOXXOX . OOOOXXXOOXXXOOOO
OOOOXXOX . OOOOXXOXXOXXOOOO
OOOOXXXO . OOOOXXOXXOXXOOOO
OOOXXXXX 8N+7 OOOOXXXOOXXXOOOO
OOOXXXXXXXXXXOOO
OOXXXXXX OOXXXXXXXXXXXXOO
OXXXXXXX OXXXXXXXXXXXXXXO
XXXXXXXX XXXXXXXXXXXXXXXX
XXXXXXXX Pattern number 1 XXXXXXXXXXXXXXXX
OOXXXXOO OOXXXXOOOOXXXXOO
OOOXXOOO OOOXXOOOOOOXXOOO
OOOOOOOO OOOOOOOOOOOOOOOO
OOOOOOOO OOOOOOOOOOOOOOOO
XOOOOOOO
XXXOOOOO
XXXXXOOO ┌────┬────┐
OXXXOOOO Pattern number 2 │ #0 │ #2 │
XOXXOOOO ├────┼────┤
XOXXOOOO │ #1 │ #3 │
OXXXOOOO └────┴────┘
XXXXXOOO
XXXXXXOO
XXXXXXXO
XXXXXXXX
XXXXXXXX Pattern number 3
OOXXXXOO
OOOXXOOO
OOOOOOOO
OOOOOOOO
- If the sprite size is 16 x 16, the pattern number specified in the sprite attribute table can be any of the numbers from #0 to #3.
2. SPRITE MODE 2 (G3, G4, G5, G6, G7)
2.1 Characteristics of SPRITE MODE 2
In SPRITE MODE 2, there are 32 sprites, numbered #0 to #31. The sprites assigned the lower numbers have a higher priority. On a single CRT horizontal line, up to 8 sprites with the highest priority are displayed, and the overlapping portions of sprites with lower priorities are not displayed.
┌────────────────────────────────────────────────┐
│ │
│ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │
│ │#0│ │#1│ ┌──┐ ┌──┐ │#4│ │#5│ │#6│ ┌──┐ :#8:.. │
│ └──┘ └──┘ │#2│ │#3│ └──┘ └──┘ └──┘ │#7│ :..#9: │
│ └──┘ └──┘ └──┘ └──┘ │
│ │
│ │
│ │
│ │
│ │
│ │
└────────────────────────────────────────────────┘
When two sprites collide (their solid portions have overlapped), this condition may be detected since bit 5 of status register S#0 is set to 1. When this occurs, the coordinates of the collision will be set in status registers S#3 to S#5.
In addition, if there are nine or more sprites on one horizontal line, bit 6 of status register S#0 will be set to 1, and the lower-order five bits will be set to the number of the ninth sprite.
The colors of the sprite may be specified for each horizontal line.
The sprite properties may be cancelled by setting the CC bit of the attribute table, and if sprites overlap, a logical OR may be done on the colors of the sprite. In other words, in SPRITE MODE 1, while only two colors may be displayed, in SPRITE MODE 2, four colors may be displayed.
2.2 SPRITE MODE 2 display (G3, G4, G5, G6, G7)
To display sprites, use the following controls.
-
Sprite size R#1 bit 1
SI = 1: 16 x 16 dots
SI = 0: 8 x 8 dots -
Sprite magnification R#1 bit 0
MAG = 1: Double-size
MAG = 0: Normal -
Sprite display R#8 bit 3
SPD = 1: Disable
SPD = 0: Enable - Setting the sprite pattern generator table
Set the sprite’s pattern in the Sprite Pattern Generator Table of the VRAM (#0 to #255). - Setting the sprite color table
Set the sprite’s color, EC, CC and IC in separate lines of the Sprite Color Table of the VRAM. - Setting the sprite attribute table
Set the sprite’s attributes (its coordinates, pattern number, and colors) in the Sprite Attribute Table of the VRAM (#0 to #31).
2.3 Relationships between the VRAM tables (G3, G4, G5, G6, G7)
Sprite Sprite Sprite Pattern
Color Table Attribute Table Generator Table
│ │ │ │ │ │
0 ├─────────────┤ ├─────────────┤ Base ├─────────────┤
│ │ │ #0 (4 bytes)│ Address │ Pattern #0 │
│ #0 │ 4 ├─────────────┤ │ (8 bytes) │
│ (16 bytes) │ │ #1 (4 bytes)│ 8 ├─────────────┤
│ │ 8 ├─────────────┤ All possible │ Pattern #1 │
│ │ . . combinations │ (8 bytes) │
16 ├─────────────┤ . . 16 ├─────────────┤
│ │ . . │ Pattern #2 │
│ #1 │ . . │ (8 bytes) │
│ (16 bytes) │ . . 24 ├─────────────┤
│ │ . . . .
│ │ . . . .
32 ├─────────────┤ . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
496 ├─────────────┤ │ │ │ │
│ │ │ │ │ │
│ #31 │ │ │ │ │
│ (16 bytes) │ │ │ 2040 ├─────────────┤
│ │ 124 ├─────────────┤ │ Pattern #255│
│ │ │#31 (4 bytes)│ │ (8 bytes) │
512 ├─────────────┤ 128 ├─────────────┤ 2048 ├─────────────┤
│ │ │ │ │ │
2.4 Sprite Attribute Table (G3, G4, G5, G6, G7)
The Sprite Attribute Table is an area of the VRAM that contains the display (x- and y-) coordinates, and pattern numbers of the 32 sprites. Each sprite has four bytes of attribute data.
| MSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | LSB |
|---|---|---|---|---|---|---|---|---|---|
| Y-coordinate (0 to 255) | ┐ Sprite attribute table base address | ||||||||
| X-coordinate (0 to 255) | │ | ||||||||
| Pattern number (0 to 255) | ├── Attribute area for sprite #0 | ||||||||
| Reserved | ┘ | ||||||||
| ┬── Attribute area for sprite #1 | |||||||||
| ┤ | |||||||||
| ┆ ├── Attribute area for sprite #1 |
|||||||||
| ┘ | |||||||||
-
Y-coordinate (0 to 255)
Specify the y-coordinate of the sprite
If the value for the sprite’s y-coordinate is set to 216, all sprites with lower priority will not be displayed. For example, if sprite #10’s y-coordinate is set to 216, sprites #10 to #31 will not be displayed. -
X-coordinate (0 to 255)
Specify the x-coordinate of the sprite. -
Pattern number (0 to 255)
Specify the sprite pattern number in the sprite pattern generator table. If the size of the sprite is 16 x 16, there will be four sprite pattern numbers corresponding to one sprite. In this case, you may specify any one of the four sprite pattern numbers.In the above manner, if all sprites are 8 x 8, there will be 256 possible patterns; however, if all sprites are 16 x 16, there will be 64 possible patterns.
┌── This bit is always set to 1. │ ┌───┬───┬───┬───┬───┬─┴─┬───┬───┐ R#5 │A14│A13│A12│A11│A10│A9 │ 1 │ 1 │ Sprite attribute table ╞═══╪═══╪═══╪═══╪═══╪═══╪═══╪═══╡ R#11 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │A16│A15│ base address register └───┴───┴───┴───┴───┴───┴───┴───┘
2.5 Sprite Pattern Generator Table (G3, G4, G5, G6, G7)
The Sprite Pattern Generator Table is an area in the VRAM to specify the sprite patterns (its appearance). The beginning (head) address of this area must be specified in register R#6 (Sprite Pattern Generator Table Base Address Register).
The pattern for each sprite must be written in this area. Eight bytes are used for each pattern, for a total of 256 patterns. Each of the 256 patterns are assigned a sprite pattern number from #0 to #255; if the sprite size is 8 x 8 dots, each sprite has one pattern and if the sprite size is 16 x 16 dots, each sprite has four patterns.
VRAM
│ ◄── 1 byte ──► │
├────────────────┤ ─┐ Sprite Pattern Generator Table
│ │ │ Base Address
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ├── Pattern #0
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ─┤
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ├── Pattern #1
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ │
│ │ │
├────────────────┤ ─┤
¦ . ¦ │
¦ . ¦
│ │ Pattern #255 (Maximum)
├────────────────┤
│ │
PART 2
MSX-VIDEO DATA PROCESSOR
LSI DATA SHEET
APPENDIX
4. Usage of unused pins
-
Output pins
All unused output pins may be left open.
-
Input or input/output pins
*DLCLK (3) Pull up with a resistor HSYNC (5) Open CSYNC (6) Open C7 to C0 (12) to (19) Open *LPS (26) Connect with VCC *LPD (27) Connect with VCC VBB (33) Open or connect to GND (1) through a capacitor
5. Cycle mode
The V9938 has three cycle modes, which may be specified according to the following settings of bits S0 and S1 in register #9.
| S 1 0 |
Cycle mode | Screen mode | HSYNC | *YS | fH | |
|---|---|---|---|---|---|---|
| High level | Low level | |||||
| 0 0 | 0 | PC only | Burst flag | H counter reset input | Low | fXTAL/1368 |
| 0 1 | 1 | Mixed | HSYNC | H counter reset input | High/Low | fXTAL/1365 |
| 1 0 | 2 | Ext. Video | HSYNC | H counter reset input | High | fXTAL/1365 |
8. Color palette
The color palette is set as shown in the table when a RESET is done. This table has no meaning in G7 mode since the color palette is not used.
In addition, since there are only four colors available in G5 mode, values from 4 to F have no meaning.
In this table, 0 means that the GRB intensity is 0, and 7 means that the GRB intensity is set to maximum.
| G | R | B | ||
|---|---|---|---|---|
| Color code | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | |
| 2 | 6 | 1 | 1 | |
| 3 | 7 | 3 | 3 | |
| 4 | 1 | 1 | 7 | |
| 5 | 3 | 2 | 7 | |
| 6 | 1 | 5 | 1 | |
| 7 | 6 | 2 | 7 | |
| 8 | 1 | 7 | 1 | |
| 9 | 3 | 7 | 3 | |
| A | 6 | 6 | 1 | |
| B | 6 | 6 | 4 | |
| C | 4 | 1 | 1 | |
| D | 2 | 6 | 5 | |
| E | 5 | 5 | 5 | |
| F | 7 | 7 | 7 |
9. Composite video color burst
The phase of the color burst is set according to the contents of register numbers 20, 21, and 22. These registers are initialized on the transition between Low --> High of the *Reset signal.
┌─────────┬───────────────┐
│Register │ Value upon │
│ number │ initialization│
├─────────┼───────────────┤
│ 20 │ &H 00 │
│ 21 │ &H 3B │
│ 22 │ &H 05 │
└─────────┴───────────────┘
In addition, when the values of all of the above registers are set to 00, the color burst effect may be removed.
Note: Do not set values other than those listed above in registers 20 to 22.
10. Color bus
┌──────────────────┬───────────────────────────────────────────────┐ │ │ Color bus │ │ Mode ├─────┬─────┬─────┬─────┬─────┬─────┬─────┬─────┤ │ │ 7 │ 6 │ 5 │ 4 │ 3 │ 2 │ 1 │ 0 │ ├──────────────────┼─────┼─────┼─────┼─────┼─────┼─────┼─────┼─────┤ │ Text I, II │ │ │ │ │ │ │ │ │ │ Multicolor │ X │ X │ X │ X │ CC3 │ CC2 │ CC1 │ CC0 │ │ G1 to G4 │ │ │ │ │ │ │ │ │ ├──────────────────┼─────┼─────┼─────┼─────┼─────┼─────┴─────┼─────┤ │ │ │ │ │ │ ◄─Even ─► ◄─ Odd ─► │ │ │ │ │ │ ├─────┼─────┬─────┼─────┤ │ G5 │ X │ X │ X │ X │ CC1 │ CC0 │ CC1 │ CC0 │ ├──────────────────┼─────┴─────┴─────┴─────┼─────┴─────┴─────┴─────┤ │ │ ◄────── Even ───────► │ ◄─────── Odd ───────► │ │ ├─────┬─────┬─────┬─────┼─────┬─────┬─────┬─────┤ │ G6 │ CC3 │ CC2 │ CC1 │ CC0 │ CC3 │ CC2 │ CC1 │ CC0 │ ├──────────────────┼─────┼─────┼─────┼─────┼─────┼─────┼─────┼─────┤ │ │ │ │ │ │ │ │ │ │ │ G7 │ CC7 │ CC6 │ CC5 │ CC4 │ CC3 │ CC2 │ CC1 │ CC0 │ │ │ │ │ │ │ │ │ │ │ └──────────────────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┘
The color bus is used as listed above whether doing input or output. For example, in G4 mode, the lower four bits (CC0 to CC3) output the color code. These bits must be set before the signals are placed on the color bus. In this case, the upper four bits are ignored. In addition, during input, since the lower four bits have the color code, that signal is displayed, and in DG = "1", the information is also stored in the VRAM.
When using high resolution modes such as G5 and G6 modes, the even and odd dots are handled together as in 0-1, 2-3, 4-5, etc. (This is the same during input and output).
11. Sprites in G5 mode
In the G5 mode, the static screen has a resolution of 512 dots in the horizontal direction. In addition, each pixel has two bits for the color code.
Sprites are displayed using half the resolution of a static screen. As a result, the sprite pattern has a resolution of 256 dots in the horizontal direction, and the coordinates are x = 0 to 255.
In order to display a sprite pattern as shown in Fig. 1, you must create a sprite pattern generator table as shown in Fig. 2.
0 1 2 3 4 5 6 7
┌───────────┬───┬───┬───────────┐
0 │ │A B│A B│ │
├─ ├───┼───┤ ─┤
1 │ │C D│C D│ │
├───┬───┬───┼───┼───┼───┬───┬───┤
2 │E F│E F│E F│E F│E F│E F│E F│E F│
├───┼───┼───┼───┼───┼───┼───┼───┤
3 │G H│G H│G H│G H│G H│G H│G H│G H│
├───┴───┴───┼───┼───┼───┴───┴───┤
4 │ │I J│I J│ │
├─ ├───┼───┤ ─┤
5 │ │K L│K L│ │
├─ ├───┼───┤ ─┤
6 │ │M N│M N│ │
├─ ┌───┼───┼───┼───┐ ─┤
7 │ │O P│O P│O P│O P│ │
└───────┴───┴───┴───┴───┴───────┘
Fig. 1 Sprite pattern
MSB LSB
┌───────────────────────────────┐
0 │ 0 0 0 1 1 0 0 0 │
├───────────────────────────────┤
1 │ 0 0 0 1 1 0 0 0 │
├───────────────────────────────┤
2 │ 1 1 1 1 1 1 1 1 │
├───────────────────────────────┤
3 │ 1 1 1 1 1 1 1 1 │
├───────────────────────────────┤
4 │ 0 0 0 1 1 0 0 0 │
├───────────────────────────────┤
5 │ 0 0 0 1 1 0 0 0 │
├───────────────────────────────┤
6 │ 0 0 0 1 1 0 0 0 │
├───────────────────────────────┤
7 │ 0 0 1 1 1 1 0 0 │
└───────────────────────────────┘
Fig. 2 Pattern generator table
The colors of the sprites depend on the settings of the sprite color table. The upper four bits of the color table use controls such as the Early Clock. The lower four bits are divided into two groups of two bits. The upper two-bit group is for the color of the even pixels, and the lower two-bit group is for the color of odd pixels. If the bits are set individually for each two-bit group and the two groups have different colors, the resolution for sprite colors can be considered as being 512 dots.
If the color table is written as shown in Fig. 3, the sprite pattern will be as shown in Fig. 1.
MSB LSB
┌───────────────┬───────┬───────┐
0 │ │ A │ B │
├───────────────┼───────┼───────┤
1 │ │ C │ D │
├───────────────┼───────┼───────┤
2 │ │ E │ F │
├───────────────┼───────┼───────┤
3 │ │ G │ H │
├───────────────┼───────┼───────┤
4 │ │ I │ J │
├───────────────┼───────┼───────┤
5 │ │ K │ L │
├───────────────┼───────┼───────┤
6 │ │ M │ N │
├───────────────┼───────┼───────┤
7 │ │ O │ P │
└───────────────┴───────┴───────┘
Fig. 3 Color table